Н. В. Моина ю. Б. Генина т. В. Шульженко чтение английской научнотехнической литературы
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MICROELECTRONICSSemiconductor ManufacturingThey are everywhere. From appliances to space ships, semiconductors have pervaded every fabric of our society. They have transformed the world so drastically that we have practically gone through hundreds of industrial revolutions during the last five decades. Nowadays, semiconductor devices allow machines to talk to us, and probably even understand us. They do our jobs, go where man has never gone before, and help us explore and utilize the universe around us. So overwhelming is the power of computing and signal processing today that it's difficult to believe how these can come from sand. Indeed, this world was reinvented simply by purifying sand, making it flat, and adding materials to it. This magical process of building integrated circuits from sand is now referred to as semiconductor manufacturing. Semiconductor manufacturing consists of the following steps: 1) production of silicon wafers from very pure silicon ingots; 2) fabrication of integrated circuits onto these wafers; 3) assembly of every integrated circuit on the wafer into a finished product; 4) testing and back-end processing of the finished products. Wafer fabrication generally refers to the process of building integrated circuits on silicon wafers. Prior to wafer fabrication, the raw silicon wafers to be used for this purpose are first produced from very pure silicon ingots, through either the Czochralski (CZ) or the Float Zone (FZ) method. The ingots are shaped then sliced into thin wafers through a process called wafering. The semiconductor industry has already advanced tremendously that there now exist so many distinct wafer fab processes, allowing the device designer to optimize his design by selecting the best fab process for his device. Nonetheless, all existing fab processes today simply consist of a series of steps to deposit special material layers on the wafers one at a time in precise amounts and patterns. Below is an example of what fabricating a simple CMOS integrated circuit on a wafer may entail. The first step might be to grow a p-type epitaxial layer on the silicon substrate through chemical vapor deposition. A nitride layer may then be deposited over the epi-layer, then masked and etched according to specific patterns, leaving behind exposed areas on the epi-layer, i. e., areas no longer covered by the nitride layer. These exposed areas may then be masked again in specific patterns before being subjected to diffusion or ion implantation to receive dopants such as phosphorus, forming n-wells. Silicon dioxide may then be grown thermally to form field oxides that isolate the n-wells from other parts of the circuit. This may be followed by another masking/oxidation cycle to grow gate oxide layers over the n-wells intended for p-channel MOS transistors later on. This gate oxide layer will serve as isolation between the channel and the gate of each of these transistors. Another mask and diffusion/implant cycle may then follow to adjust threshold voltages on other parts of the epi, intended for n-channel transistors later on. Deposition of a polysilicon layer over the wafer may then be done, to be followed by a masking/etching cycle to remove unwanted polysilicon areas, defining the polysilicon gates over the gate oxide of the p-channel transistors. At the same time, openings for the source and drain drive-ins are made on the n-wells by etching away oxide at the right locations. Another round of mask/implant cycle may then follow, this time driving in boron dopants into new openings of the n-wells, forming the p-type sources and drains. This may then be followed by a mask/implant cycle to form the n-type sources and drains of the n-channel transistors in the p-type epi. The wafer may then be covered with phospho-silica glass, which is then subjected to reactive ion etching in specific patterns to expose the contact areas for metallization. Aluminum is then sputtered on the wafer, after which it is subjected to reactive ion etching, also in specific patterns, forming connections between the various components of the circuit. The wafer may then be covered with glassivation as its top protective layer, after which a mask/etch process removes the glass over the bond pads. Such is the process of wafer fabrication, consisting of a long series of mask/etch and mask/deposition steps until the circuit is completed. The process of putting the integrated circuit inside a package to make it reliable and convenient to use is known as semiconductor package assembly, or simply "assembly". Over the years, the direction of assembly technology is to develop smaller, cheaper, more reliable, and more environment-friendly packages. Just like wafer fabrication technology, assembly technology has advanced tremendously that there are now a multitude of packages to choose from. Despite glaring differences between the various packages available in the industry today, all packages share some things in common. To name a few, all of them: 1) provide the integrated circuit with a structure to operate in; 2) protect the integrated circuit from the environment; 3) connect the integrated circuit to the outside world; 4) help optimize the operation of the device. In general, an assembly process would consist of the following steps: 1) die preparation, which cuts the wafer into individual integrated circuits or dice; 2) die attach, which attaches the die to the support structure (e. g., the leadframe) of the package; 3) bonding, which connects the circuit to the electrical extremities of the package, thereby allowing the circuit to be connected to the outside world; 4) encapsulation (usually by plastic molding), which provides "body" to the package of the circuit for physical and chemical protection. Subsequent steps that give the package its final form and appearance (e. g., DTFS) vary from package to package. Steps like marking and lead finish give the product its own identity, improve reliability, and add an extra shine at that. Once assembled, the integrated circuit is ready to use. However, owing to the imperfection of this world, assembled devices don't always work. Many things can go wrong to make a device fail, e. g., the die has wafer fab-related defects, or the die cracked during assembly, or the bonds were poorly connected or not connected at all. Thus, prior to shipment to the customer, assembled devices must first be electrically tested. Electrical testing of devices in big volumes must be done fast and inexpensively. Mass-production electrical testing therefore requires an automated system for doing the test. Equipment used to test devices are called, well, testers, and equipment used to handle the devices while undergoing testing are called, well, handlers. Tester/handler systems are also known as automatic test equipment (ATE). Different products require different levels of sophistication in ATE requirements. Electrical testing of voltage reference circuits certainly don't require high-end ATE such as those used to test state-of-the-art microprocessors or digital signal processors. One area of electrical testing that continuously challenge engineers is building an ATE that can test the speed of new IC's that are much faster than what they can use in building their ATE's. Software written for testing a device with an ATE is known as a test program. Test programs consist of a series of subroutines known as test blocks. Generally, each test block has a corresponding device parameter to test under specific conditions. This is accomplished by subjecting the device under test (DUT) to specific excitation and measuring the response of the device. The measurement is then compared to the pass/fail limits set in the test program. After the device is tested, the handler bins it out either as a reject or as a good unit. After a lot is tested, it is subjected to other back-end processes prior to shipment to the customer. Tape and reel is the process of packing surface mount devices in tapes with pockets while this tape is being wound around a reel. Boxing and labeling is the process of putting the reels or tubes in shipment boxes, and labeling these shipment boxes in accordance with customer requirements. Polysilicon and Its Manufacturing Thin films of polycrystalline silicon, or polysilicon (also known as poly-Si or poly), are widely used as MOS transistor gate electrodes and for interconnection in MOS circuits. It is also used as resistor, as well as in ensuring ohmic contacts for shallow junctions. When used as gate electrode, a metal (such as tungsten) or metal silicide (such as tantalum silicide) may be deposited over it to enhance its conductivity. Poly-Si is known to be compatible with high temperature processing and interfaces very well with thermal SiO2. As a gate electrode, it has also been proven to be more reliable than Al. It can also be deposited conformally over steep topography. Heavily-doped poly thin films can also be used in emitter structures in bipolar circuits. Lightly-doped poly films can also be used as resistors. Poly-Si is usually deposited by thermal decomposition or pyrolysis of silane at temperatures from 580...650 oC, with the deposition rate exponentially increasing with temperature. The deposition rate is also affected by the pressure of silane, which translates to silane concentration. Other important variables in polysilicon deposition are pressure and dopant concentration. The electrical characteristics of a poly-Si thin film depends on its doping. As in single-crystal silicon, heavier doping results in lower resistivity. Poly-Si is more resistive than single-crystal silicon for any given level of doping mainly because the grain boundaries in poly-Si hamper carrier mobility. Common dopants for polysilicon include arsenic, phosphorus, and boron. Polysilicon is usually deposited undoped, with the dopants just introduced later on after deposition. There are three ways to dope polysilicon, namely, diffusion, ion implantation, and in situ doping. Diffusion doping consists of depositing a very heavily-doped silicon glass over the undoped polysilicon. This glass will serve as the source of dopant for the poly-Si. Dopant diffusion takes place at a high temperature, i. e., 900...1000 oC. Ion implant is more precise in terms of dopant concentration control and consists of directly bombarding the poly-Si layer with high-energy ions. In situ doping consists of adding dopant gases to the CVD reactant gases during the epi deposition process. There are three commonly used techniques for doping polysilicon: 1) diffusion doping; 2) ion implantation; 3) in-situ doping. Diffusion doping is generally done at a relatively high temperature (900...1000 oC). It involves the growing or deposition of a highly-doped glass on the undoped polysilicon. This doped glass will serve as the source of dopants that will diffuse into the polysilicon material. The high-temperature environment of diffusion doping not only promotes dopant diffusion from the source, but also anneals the polysilicon material. Diffusion doping's advantage is its ability to introduce very high concentrations of dopants into the poly-Si layer, attaining low levels of resistivity. The high processing temperature and its tendency to increase surface roughness are its drawbacks. Ion implantation deposits dopants into the poly-Si layer by directly bombarding it with high-energy ions of the dopant species. Since ion implantation has destructive effects, it is followed by an annealing step that repairs the lattice disturbances and activates the implanted dopants. The advantage of ion implantation is its ability to control dopant dosage with high precision. However, it can not attain the low resistivities achievable by diffusion doping, i. e., even heavily doped ion-implanted poly-Si layers exhibit ten times the resisitivity exhibited by diffusion-doped layers. Ion-implanted polysilicon layers are often used in applications where high conductivity is not required, such as being employed as high-value load resistors in circuits. In-situ doping refers to the doping technique wherein the dopants are introduced to the poly-Si at the same time the poly-Si layer is being deposited. In-situ doping involves the addition of dopant gases such as phosphine and diborane to the CVD reactant gases used in poly-Si deposition. In-situ doping is not a simple process, since the introduction of the dopant gases complicates the control of layer thickness, dopant uniformity, and deposition rate. Adding dopants during deposition also affects the physical properties of the poly-Si layer, such as the grain size and grain orientation. Polysilicon deposition, or the process of depositing a layer of polycrystalline silicon on a semiconductor wafer, is achieved by pyrolyzing (decomposing thermally) silane, SiH4, inside a low-pressure reactor at a temperature of 580 to 650 oC. This pyrolysis process involves the following basic reaction: SiH4 → Si + 2H2. Polysilicon has many applications in VLSI manufacturing. One of its primary uses is as gate electrode material for MOS devices. A polysilicon gate's electrical conductivity may be increased by depositing a metal (such as tungsten) or a metal silicide (such as tungsten silicide) over the gate. Polysilicon may also be employed as a resistor, a conductor, or as an ohmic contact for shallow junctions, with the desired electrical conductivity attained by doping the polysilicon material. There are two common low-pressure processes for depositing polysilicon layers: using 100 % silane at a pressure of 25...130 Pa (0.2 to 1.0 Torr), and using 20–30 % silane (diluted in nitrogen) at the same total pressure. Both of these processes can deposit polysilicon on 10–200 wafers per run, at a rate of 10...20 nm/min and with thickness uniformities of ±5 %. The critical process variables for polysilicon deposition include temperature, pressure, silane concentration, and dopant concentration. Wafer spacing and load size have been shown to have only minor effects on the deposition process. The rate of polysilicon deposition increases rapidly with temperature. There will be a minimum temperature, however, wherein the rate of deposition becomes faster than the rate at which unreacted silane arrives at the surface. Beyond this temperature, the deposition rate can no longer increase with temperature, since it is now being hampered by lack of silane from which the polysilicon will be generated. Such a reaction is then said to be "mass-transport-limited". When a polysilicon deposition process becomes mass-transport-limited, the reaction rate becomes dependent primarily on reactant concentration, reactor geometry, and gas flow. When the rate at which polysilicon deposition occurs is slower than the rate at which unreacted silane arrives, it is said to be surface-reaction-limited. A deposition process that is surface-reaction-limited is primarily dependent on reactant concentration and reaction temperature. Deposition processes must be surface-reaction-limited because they result in excellent thickness uniformity and step coverage. At reduced pressure levels for VLSI manufacturing, polysilicon deposition rate below 575 oC is too slow to be practical. Above 650 oC, poor deposition uniformity and excessive roughness will be encountered due to unwanted gas-phase reactions and silane depletion. Pressure can be varied inside a low-pressure reactor either by changing the pumping speed or changing the inlet gas flow into the reactor. If the inlet gas is composed of both silane and nitrogen, the inlet gas flow, and hence the reactor pressure, may be varied either by changing the nitrogen flow at constant silane flow, or changing both the nitrogen and silane flow to change the total gas flow while keeping the gas ratio constant. Polysilicon doping, if needed, is also done during the deposition process, usually by adding phosphine, arsine, or diborane. Adding phosphine or arsine results in slower deposition, while adding diborane increases the deposition rate. The deposition thickness uniformity usually degrades when dopants are added during deposition. |